Ultra-High Density MEMS-Based Interconnect for Wafer-Level Ultra-Thin Die Stacking Technology

This work describes a novel smart three axis compliant (STAC) interconnect targeted to revolutionize chipto-chip and chip-to-board high-density three dimensional (3D) integration for ultra-thin Si dies (≤ 75 μm) at the wafer level. The STAC interconnect is a 3D-compliant interconnect which allows stacked ultra-thin chips to move or flex freely during operation with negligible stress imposed on the die. The work shows that these interconnects can possibly accommodate mismatches of board or package coefficient of thermal expansion (CTE) from chip CTE. STAC interconnects are fabricated using MEMS technologies to support super-finepitch (≈ 20 μm pitch) interconnection. These interconnects are batch processed and die containing them can be stacked either at the wafer-level or at the die-level.